diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 09aa97e..42280cb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -185,7 +185,7 @@
 config CLK_VERSAL
 	bool "Enable clock driver support for Versal"
 	depends on (ARCH_VERSAL || ARCH_VERSAL_NET)
-	select ZYNQMP_FIRMWARE
+	imply ZYNQMP_FIRMWARE
 	help
 	  This clock driver adds support for clock realted settings for
 	  Versal platform.
@@ -219,7 +219,7 @@
 config CLK_ZYNQMP
 	bool "Enable clock driver support for ZynqMP"
 	depends on ARCH_ZYNQMP
-	select ZYNQMP_FIRMWARE
+	imply ZYNQMP_FIRMWARE
 	help
 	  This clock driver adds support for clock realted settings for
 	  ZynqMP platform.
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 61490d6..62cb77b 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -75,7 +75,7 @@
 
 config FPGA_ZYNQMPPL
 	bool "Enable Xilinx FPGA driver for ZynqMP"
-	depends on FPGA_XILINX
+	depends on FPGA_XILINX && ZYNQMP_FIRMWARE
 	help
 	  Enable FPGA driver for loading bitstream in BIT and BIN format
 	  on Xilinx Zynq UltraScale+ (ZynqMP) device.
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 91e309d..8b559d8 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -988,7 +988,7 @@
 };
 #endif
 
-#if defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
 static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
 					   struct udevice *dev)
 {
@@ -1090,7 +1090,7 @@
 
 	host = priv->host;
 
-#if defined(CONFIG_ARCH_ZYNQMP)
+#if defined(CONFIG_ARCH_ZYNQMP) && defined(CONFIG_ZYNQMP_FIRMWARE)
 	if (device_is_compatible(dev, "xlnx,zynqmp-8.9a")) {
 		ret = zynqmp_pm_is_function_supported(PM_IOCTL,
 						      IOCTL_SET_SD_CONFIG);
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index cc49788..211b2c6 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -738,7 +738,7 @@
 	u32 pm_info[2];
 	int ret;
 
-	if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
+	if (IS_ENABLED(CONFIG_ARCH_ZYNQMP) && IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
 		if (!zynqmp_pm_is_function_supported(PM_IOCTL,
 						     IOCTL_SET_GEM_CONFIG)) {
 			ret = ofnode_read_u32_array(dev_ofnode(dev),